OB => aUserGpio_n(61), - Diff_n output (connect directly to top-level port)ĪDC2_CNV_buf ADC2_FSM ADC2_FSM ADC2_FSM Įlsif UserGClk2'event and UserGClk2='0' then - the host uses the rising edge of DCO± to capture D± O => aUserGpio(61), - Diff_p output (connect directly to top-level port) Part of my vhd clip file (cause it's too large and all other LVTTL logic works fine except LVDS):Īttribute dont_touch of ADC2_CNV_buf : signal is "true" My xdc file ( aUserGpio(61) and aUserGpio_n(61) belong to Bank 18) : Is it possible to use pins which is not clock capable to output LVDS or I am doomed to use MRCC or SRCC pins? With Kintex-7 it compiles without errors but i didn't see signals on pins aUserGpio(61) and aUserGpio_n(61), although ADC2_FSM is switching its state. These pins are not K7 clock capable, but I used this FLEX RIO module with PXIe-7962R (Virtex-5 FPGA) where these pins are REGIONAL clock capable and it worked fine. I have a problem trying to output LVDS signal via aUserGpio(61) and aUserGpio_n(61). ![]() I've developed a custom FLEX RIO module (Digitizer18, 0xAB66 - vendor id) and trying to use it with PXIe-7975R FPGA card (Kintex-7 FPGA)
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